[feat](trx-vdes): implement Turbo FEC, CRC-16, and link-layer parsing
Add the three missing VDES decoder components per ITU-R M.2092-1: - turbo.rs: Turbo FEC decoder with dual 8-state RSC constituent encoders, BCJR/MAP iterative decoding (8 iterations), QPP interleaver, and rate-1/2 depuncturing - crc.rs: CRC-16-CCITT validation (poly 0x1021, init 0xFFFF) for decoded link-layer frames - link_layer.rs: Structured parsing of M.2092-1 link-layer frames (Messages 0-6) including station addressing, ASM identification, geographic bounding boxes, and ACK/NACK reporting The main decode pipeline now attempts turbo decoding first with CRC validation, falls back to Viterbi when turbo fails, and reports crc_ok=true when either path validates. 27 tests covering all new modules. https://claude.ai/code/session_01SJSN7cv3zoL1xNcb8ex2zY Signed-off-by: Claude <noreply@anthropic.com>
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@@ -147,7 +147,7 @@ Improvement plan: `docs/Improvement-Areas.md`
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**P3 — Low:**
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- **Missing tests**: `audio.rs` (3,812 LOC), `api.rs` (2,711 LOC), `main.rs` (1,203 LOC) have 0 tests.
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- **FT-817 VFO inference fragile**: Fails when VFO A and B share the same frequency.
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- **VDES decoder incomplete**: Turbo FEC, CRC, and link-layer parsing not implemented.
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- ~~**VDES decoder incomplete**~~: Turbo FEC, CRC-16, and M.2092-1 link-layer parsing now implemented.
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- **Plugin system lacks versioning**: No API version or reload semantics.
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- **Configurator detection stubbed**: `detect.rs` TODO for `serialport::available_ports()`.
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- **Inconsistent naming**: `freq_hz`/`frequency`/`center_hz`; `rig_id`/`id`; `model`/`rig_model`.
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