[fix](trx-backend-soapysdr): disable hidden AIS DSP outside AIS modes

Add per-channel processing gating and disable hidden AIS channel DSP unless mode is AIS or MARINE, reducing continuous IQ read-loop CPU load in normal operation.\n\nCo-authored-by: OpenAI Codex <codex@openai.com>

Signed-off-by: Stan Grams <sjg@haxx.space>
This commit is contained in:
2026-03-05 22:01:21 +01:00
parent 9ed93ec0fa
commit 5dcc117e61
2 changed files with 26 additions and 2 deletions
@@ -86,6 +86,7 @@ pub struct ChannelDsp {
iq_agc: Option<SoftAgc>, iq_agc: Option<SoftAgc>,
audio_agc: SoftAgc, audio_agc: SoftAgc,
audio_dc: Option<DcBlocker>, audio_dc: Option<DcBlocker>,
processing_enabled: bool,
} }
impl ChannelDsp { impl ChannelDsp {
@@ -262,9 +263,14 @@ impl ChannelDsp {
iq_agc: iq_agc_for_mode(mode, channel_sample_rate), iq_agc: iq_agc_for_mode(mode, channel_sample_rate),
audio_agc: agc_for_mode(mode, audio_sample_rate), audio_agc: agc_for_mode(mode, audio_sample_rate),
audio_dc: dc_for_mode(mode), audio_dc: dc_for_mode(mode),
processing_enabled: true,
} }
} }
pub fn set_processing_enabled(&mut self, enabled: bool) {
self.processing_enabled = enabled;
}
pub fn set_mode(&mut self, mode: &RigMode) { pub fn set_mode(&mut self, mode: &RigMode) {
self.mode = mode.clone(); self.mode = mode.clone();
if *mode != RigMode::WFM { if *mode != RigMode::WFM {
@@ -325,6 +331,9 @@ impl ChannelDsp {
} }
pub fn process_block(&mut self, block: &[Complex<f32>]) { pub fn process_block(&mut self, block: &[Complex<f32>]) {
if !self.processing_enabled {
return;
}
let n = block.len(); let n = block.len();
if n == 0 { if n == 0 {
return; return;
@@ -227,7 +227,7 @@ impl SoapySdrRig {
let spectrum_buf = pipeline.spectrum_buf.clone(); let spectrum_buf = pipeline.spectrum_buf.clone();
let retune_cmd = pipeline.retune_cmd.clone(); let retune_cmd = pipeline.retune_cmd.clone();
Ok(Self { let rig = Self {
info, info,
freq: initial_freq, freq: initial_freq,
mode: initial_mode, mode: initial_mode,
@@ -245,7 +245,9 @@ impl SoapySdrRig {
gain_db, gain_db,
max_gain_db, max_gain_db,
ais_channel_indices: Some((primary_channel_count, primary_channel_count + 1)), ais_channel_indices: Some((primary_channel_count, primary_channel_count + 1)),
}) };
rig.apply_ais_channel_activity();
Ok(rig)
} }
/// Simple constructor for backward compatibility with the factory function. /// Simple constructor for backward compatibility with the factory function.
@@ -300,6 +302,18 @@ impl SoapySdrRig {
} }
} }
fn apply_ais_channel_activity(&self) {
let Some((ais_a_idx, ais_b_idx)) = self.ais_channel_indices else {
return;
};
let enabled = matches!(self.mode, RigMode::AIS | RigMode::MARINE);
for idx in [ais_a_idx, ais_b_idx] {
if let Some(dsp_arc) = self.pipeline.channel_dsps.get(idx) {
dsp_arc.lock().unwrap().set_processing_enabled(enabled);
}
}
}
pub fn subscribe_iq_channel( pub fn subscribe_iq_channel(
&self, &self,
channel_idx: usize, channel_idx: usize,
@@ -435,6 +449,7 @@ impl RigCat for SoapySdrRig {
dsp.set_mode(&mode); dsp.set_mode(&mode);
dsp.set_filter(self.bandwidth_hz, self.fir_taps as usize); dsp.set_filter(self.bandwidth_hz, self.fir_taps as usize);
} }
self.apply_ais_channel_activity();
self.apply_ais_channel_filters(); self.apply_ais_channel_filters();
Ok(()) Ok(())
}) })